Q. What are the features of VHDL?
Q. What are the different types of modeling in VHDL?
Q. What is port mapping and how is it done?
Q. What is the use of foreign attribute in VHDL?
Q. What are VITAL functions? (VHDL Initiative Towards ASIC Libraries)
Q. Can any design be implemented using any of the design models in VHDL?
Q. Process is a concurrent statement. (TRUE/FALSE) Justify?
Q. What is the use of Assertion statement?
Q. What do you mean by generic mapping and what is the use of it?
Q. Explain generate statement?
Q. Define subprogram?
Q. What is the difference between a procedure and a function?
Q. Differentiate between operators overloading and function overloading?
Q. Difference between exit and next statements?
Q. What is aliasing? Give an example?
Q. What is an attribute? Name some of the predefined attributes?
Q. Implement a full adder using two half adders?
Q. What is the difference between inertial delay and transport delay?
Q. Explain generate statement?
Q. Define a package?
Q. Write a VHDL code for DFF with asynchronous RESET?
Q. Expand PSPICE?
Q. What is BLOCK statement?
Q. How do you detect if two 8-bit signals are same?
Q. How do you detect a sequence of “1101″ arriving serially from a signal line?
Q. What are the two key concepts in the simulation semantics of VHDL and how does each concept help VHDL simulation produce waveforms that match the behaviour that we expect?
Q. What is the advantage of RTL simulation in comparison to simulation as defined by the VHDL standard?
Q. What is the disadvantage of RTL simulation in comparison to simulation as defined by the VHDL standard?
Q. For a combinational process in VHDL, the sensitivity list should contain all of the signals that are read in the process. Please give a detailed reason and an exception to this statement.
Q. For a combinational process, every signal that is assigned to, must be assigned to in every branch of If-Then-Else statement and Case statement. Why?
Q. Each signal should be assigned to in only one process. Please give a detailed reason and an exception to this statement.
Q. Separate unrelated signals into different processes. Give atleast two reasons!
Q. In a state-machine, illegal and unreachable states should transition to the reset state. Explain.
Q. If your state-machine has less than 16 states, use a one-hot encoding. Explain.
Q. Include a reset signal in all clocked circuits. Explain.
Q. For implicit state-machines, check for reset after every wait statement.
Q. Connect reset to the important control signals in the design, such as the state signal. Do-not reset every flip-flop. Explain.
Q. Discuss the subtypes with examples as are used in VHDL.
Q. What is key difference between sequential and combinational circuits?
Q. Design BCD to Excess-3 code convertor, using minimum number of NAND gates.
Q. Discuss the Physical types with examples as used in VHDL.
Q. Discuss the Difference between array and records types.
Q. What is meant by operator overloading? Give an example.
Q. what is the difference between function and procedure in VHDL? Give suitable examples.
Q. Discuss the use of function as a type conversion function.
Q. Write down the truth table, entity declaration and behavioural/dataflow architecture for the Encoder. Also draw the circuit and output waveforms
Q. Write down the truth table and VHDL code for the 4-bit left to right shift register. Also draw the circuit and output waveforms.
Q. Write down the truth table and VHDL code for the 4-bit up/down counter. Also draw the circuit and output waveforms
Q. What are the basic components of a micro computer? Explain briefly.
Q. Describe microcomputer implementation in VHDL.
Q. How can a ROM be used as a PLA’) Write down its advantages.
Q. Discuss briefly 22 V /0 PLD.
Q. Write short note on PAL 16L8.
Q. Write short note on Various Loops in VHDL
Q. Write short note on Packages.
Q. What is the difference between variable and signal.
Q. Design a 2 to 4 decoder circuit. Give its entity declaration and structural model and behavioural model. Also draw the waveform giving relation between its inputs and outputs.
Q. Write short note on difference between if and case statement.
Q. Write short note on Loop statement.
Q. Write short note on Next statement.
Q. Write down truth table, working behavioural / dataflow ·architecture for the Code convertor. Also draw the circuit and output waveform.
Q. Write down truth table, working behavioural / dataflow architecture for the 4-bit comparator. Also draw the circuit and output waveform.
Q. Write down truth table, VHDL Code for the n bit register with parallel load. Also draw the circuit and output waveform.
Q. Write down truth table, VHDL Code for the J-K flip flop using behavioral modeling.
Q. What are basic components of computer. Write down VHDL code for memory sub system.
Q. Write short note on FPGA.
Q. Differentiate between a process and wait statement. Can they be used simultaneously in a program?
Q. Write down the VHDL code for D-FF, and T-FF?
Q. Write down the VHDL code of S-R flip flop.
Q. What are generics?
Q. Expalin with example that how a component can be made more general using generics?
Q. What are sequential statements? Write down its syntax.
Q. Discuss process and wait statements.
Q. How are sequential statements different from concurrent statements ?
Q. Write a short note on package and library.
Q. Write down the VHDL code for ALU and describe its working. Briefly explain the function of control unit.
Q. Design a BCD-to-excess-3 code converter using PLA and PAL.
Q. Write short notes on Conditional statements.
Q. Write short notes on Case statements.
Q. What are basic components of a computer. Write down the code for memory or input / output subsystem.
Q. Write down the truth table; working of a 16 x 1 multiplexer along with its diagram. Implement 16 x 1 multiplexer in VHDL using case statement.
Q. Write short notes on Arrays and loops.
Q. Write short notes on Structural Modelling.
Q. What is the difference between encoder and multiplexer.
Q. What is the difference between decoder and demultiplexer.
Q. What are steps involved in implementation and anlysis of digital systems.
Q. What are capabilities of VHDL.
Q. Explain the significance of conditional signal assignment statement and selected signal assignment statement.
Q. How will you compare component declaration and component instantiation.
Q. Write down the configuration specification for full adder circuit.
Q. Write short note on subprogram.
Q. What are aliases. Expalin with example.
Q. Design and implement counter using VHDL which counts upto 9 and down counts again from 9 to 0.
Q. Explain resolution functions.
Q. How does look-a head carry adder speed up the addition process.
Q. What is parity bit generator.
Q. What are applications of flip flops.
Q. What is shift register. Write the VHDL code of Shift register.
Q. Give logic diagram of 4-bit buffer register.
Q. What are different types of ROM,s.
Q. What is the disadvantage of serial adder. For which applications are they preffered.
Q. Wgat is difference between counting sequence of an up-counter and down-counter.
Q. Design and implement Mod6 counter using T-flip flop.
Q. Design and implement Mod3 counter using J-K-flip flop.
Q. What are applications of shift register.
Q. Design and implement 4-bit gray to binary converter.
Q. What are hardware description languages.
Q. Design and implement Mod5 counter using D-flip flop.
Q. Write short note on delta delay.
Q. What are different computer aided tools for digital systems.
Q. What are applications of multiplexers.
Q. Write short note on inertial delay.
Q. What do you mean by latch and gated latch.
Q. How does PLA differ from ROM.
Q. How do you convert one type of flip flop to another
Q. Write short note on transport delay.
Q. Write about behavioral models.
Q. How do you convert S_R flip flop to J-K flip flop.
Q. Deign and implement synchronous 3-bit up/down counter using J-K flip flops.
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